A+ Topic: RAM

RAM: Packaging, clocking, naming and more

 

The following detailed article was provided by Kirk L. Mason:

Computers have used many forms of memory over the years. Some may remember drum, core, and bubble memory. Since the introduction of the Personal Computer in 1981, computer memory has settled into a utilization of semiconductor based forms of ROM and RAM.

ROM and RAM can be found in both asynchronous and synchronous packages.

Asynchronous simply means that there is no synchronization between the address and the data lines of the device: The device is presented with an address and the proper control signals (read/write, Chip Select, Output Enable/Disable) and the data is either presented to or accepted from the data bus.

Synchronous means that everything is synchronized to a common trigger point on a clock signal. Trigger points can be when the clock signal is high, low, or transitioning to a high or low state., or combination of any of the above. All that is required is that the inputs be stabilized by the time the trigger condition is reached.

ROM or Read Only Memory

ROM is not the topic of this page, but I have included a dissertation at the end for those interested.

RAM or Random Access Memory

RAM is used throughout today’s computers.

Static RAM (or SRAM) is fast compared to Dynamic RAM (DRAM) but considerably more complex. SRAM is simple to access; you set an address on the bus, set its control pins (read, write, select) and the data is either presented to or read from the data bus. Static memory is stable as long as the device is given power.

Dynamic RAM (DRAM) is much simpler to manufacture but considerably more complex to operate. Between the read and write cycles the memory controller must “refresh” the data stored in each cell. Modern DRAM devices are able to manage this function automatically. The memory controller simply applies the appropriate command to the DRAM and provides the necessary number of clock pulses. Each refresh cycle requires that all banks of internal memory be idle and will refresh one row of data across all internal memory banks. It is typical that a refresh cycle be conducted each 64ms. Because DRAM was so slow it was common for early PC processors to be given wait states after each memory request to allow the memory subsystem sufficient time to service the memory request.

The smallest capacity RAM device is typically found on the motherboard’s CMOS RAM where the system battery maintains configuration data. CMOS RAM (also called Non-Volatile or NVRAM) ranged in size from the early 64B Motorola devices to the more current 2MB STMicroelectronics devices. A typical CMOS memory map can be seen here.

Medium capacity RAM is found in devices such as the CPU cache (12MB for the current Intel i7-980X), disk drive cache (32MB for the current Seagate Barracuda line) and Video Adapters (up to 6GB for some current high end NVidia Quadro 6000 adapters) .

When people speak of computer memory they are commonly speaking of system memory. This is memory used by the CPU to run applications and services.

Early PCs were limited by Microsoft DOS (Disk Operating System) to 640KB. The original PCs were based on the Intel 8086 processor which was a 16 bit processor with a 20 bit external address bus. These attributes limited the total address capacity to 1MB of which the processor could actively address only 64KB at a time. Today’s processors use a 64 bit architecture and a 64 bit address bus capable of addressing 264 bytes or roughly 18.5 Exabyte (EB) of memory Current Windows platforms limit system memory to 2TB for some 64bit versions of Server2008, but are more typically limited to 16GB for Windows 7 Home Premium and 192GB for versions above that level.

Enough on the history and variations of PC memory, the information to follow concerns the actual hardware of the PC system memory

An essay on early PC memory hardware can be found at http://www.philipstorr.id.au/pcbook/book2/memchips.htm.

Computer memory can generally be broken down into :

Single Inline Memory Module (SIMM)

30 pin:

30 pin SIMMs are electronically the same on each side of the contact (if the PCB was plated on both sides).

30pinSIMM.jpg

30-pin SIMMs have 12 address lines, which can provide a total of 24 address bits. An 8 bit data width (1 Byte wide) leads to an absolute maximum capacity of 16 MB.

 

Size in BYTES

30-Pin SIMM, Non-Parity

30-Pin SIMM, Parity

256 KB

256Kx8

256Kx9

512 KB

512Kx8

512Kx9

1 MB

1Mx8

1Mx9

2 MB

2Mx8

2Mx9

4 MB

4Mx8

4Mx9

8 MB

8Mx8

8Mx9

16 MB

16Mx8

16Mx9

72 pin:

72 pin SIMMs are not electronically the same on each side of the contact. This allows for dual sided SIMMs acting as if two single sided SIMMs were adhered back to back. Keep in mind that some motherboards, seeing both sides uniquely, may not accept memory inserted into all memory slots. A dual sided SIMM may be counted as two SIMMs.

32 MB 72-pin SIMM RAM

 

72-pin SIMMs have 12 address lines, which can provide a total of 24 address bits. A 32 bit data width (4 Bytes wide) leads to an absolute maximum capacity of 64 MB.

 

Size in BYTES

72-Pin SIMM, Non-Parity

72-Pin SIMM, Parity/ECC

1 MB

256×32

256×36

2 MB

512×32

512×36

4 MB

1×32

1×36

8 MB

2×32

2×36

16 MB

4×32

4×36

32 MB

8×32

8×36

64 MB

16×32

16×36

72 pin SIMMs also include FPM, EDO, and BEDO DRAM:

Fast page mode DRAM is also called FPM DRAM, Page mode DRAM, Fast page mode memory, or Page mode memory.

In page mode, a row of the DRAM can be kept “open” while performing multiple reads or writes so that successive reads or writes within the row do not suffer the delay of precharge and accessing the row. This increases the performance of the system when reading or writing bursts of data.

Extended Data Out or EDO DRAM, sometimes referred to as Hyper Page Mode enabled DRAM, is similar to Fast Page Mode DRAM with the additional feature that a new access cycle can be started while keeping the data output of the previous cycle active. It was 5% faster than Fast Page Mode DRAM, which it began to replace in 1995.

Burst Extended Data Out or BEDO DRAM is created when EDO DRAM is combined with pipelining technology and special latches to allow for much faster access time than regular EDO DRAM. Intel chose not to support BEDO memory in its chipset turning instead to SDRAM. Hence, BEDO memory did not gain much market share.

D ual Inline Memory Module (DIMM)

168 pin:

Synchronous DRAM (SDRAM. Later renamed Single Data Rate SDRAM or SDR SDRAM) operates in lock-step with the system’s clock. The memory clock speed is referred to as the Front Side Bus (FSB). A system clock of 100MHz produced a FSB clock of 100MHz. and one cycle of the system clock yielded one word of data. These memory devices were referred to as PC66, PC100, or PC133 depending on the corresponding FSB.

168 pin DIMM

168-pin DIMMs have two notches. The pin out diagram shows 13 address lines which can be multiplexed into a row and column address of a matrix. It also shows a data bus of 64 bits.

184 pin:

Double Data Rate RAM (DDR-RAM) is very similar to SDR SDRAM except that it operates at a lower voltage and will produce two words or data per clock cycle and is capable of producing subsequent sequential data addresses at a rate of two per clock cycle. A system clock of 100MHz produced a FSB clock of 200MHz and one cycle of the system clock produced two sequential words of data.

184 pin DDR

184-pin DIMMs have one notch. The pin out diagram shows 13 address lines which can be multiplexed into a row and column address of a matrix. It also shows a data bus of 64 bits.

240 pin:

DDR2 RAM once again doubled the output of the device and lowered the operational voltage. DDR2 devices will produce four words or data per clock cycle and is capable of producing subsequent sequential data addresses at a rate of four per clock cycle. A system clock of 100MHz produced a FSB clock of 400MHz and one cycle of the system clock produced four sequential words of data.

DDR3 RAM doubled again the output of the DDR2 device and again lowered the operational voltage. DDR3 devices will produce eight words or data per clock cycle and is capable of producing subsequent sequential data addresses at a rate of eight per clock cycle. A system clock of 100MHz produced a FSB clock of 800MHz and one cycle of the system clock produced eight sequential words of data.

DDR4 RAM is expected to hit the market in 2012 and be a doubling of the DDR3 device and also lower the operational voltage. DDR4 devices will produce 16 words or data per clock cycle and is capable of producing subsequent sequential data addresses at a rate of 16 per clock cycle. A system clock of 100MHz produced a FSB clock of 1600MHz and one cycle of the system clock produced 16 sequential words of data.

240 pin DDR

240-pin DIMMs have one notch. The notch location changes with each version of the DDR specification because the operational voltage is reduced. DDR4 is not physically nor electronically compatible with DDR3, which is not compatible with DDR2. The pin out diagram shows 13 address lines which can be multiplexed into a row and column address of a matrix. It also shows a data bus of 64 bits.

144 pin:

Micro-DIMM

144 pin Micro-DIMM

200 pin:

SO-DIMM

144 pin Micro-DIMM

 

DDR Naming Conventions and Characteristics

Standard name

Memory clock

Front Side Bus

Transactions per cycle

Peak transfer rate

Module name

Cm

FSB

T

Cm*T*8

(MHz)

(MHz)

(MB/s)

DDR-200

100

200

2

1600

PC-1600

DDR-266

133

266

2

2128

PC-2100

DDR-333

166

332

2

2656

PC-2700

DDR-400

200

400

2

3200

PC-3200

 

 

 

 

 

 

DDR2-400

100

400

4

3200

PC2-3200

DDR2-533

133

532

4

4256

PC2-4200

DDR2-667

166

664

4

5312

PC2-5300

DDR2-800

200

800

4

6400

PC2-6400

DDR2-1066

266

1064

4

8512

PC2-8500

 

 

 

 

 

 

DDR3-800

100

800

8

6400

PC3-6400

DDR3-1066

133

1064

8

8512

PC3-8500

DDR3-1333

166

1328

8

10627

PC3-10600

DDR3-1600

200

1600

8

12800

PC3-12800

DDR3-1866

233

1864

8

14912

PC3-14900

DDR3-2133

266

2128

8

17024

PC3-17000

 

ROM or Read Only Memory

ROM is fast, non-volatile memory which does not require battery backup as does CMOS RAM. Think of the evolution of a Compact Disk (CD). Originally, only the manufacturer had the capability to create a CD. Later, some bright soul figured out a way to sell blank CDs (CD-R) and let you “burn” your own. If you burned it wrong it was discarded and another was burned. Eventually, re-writable CDs (CD-RW) were developed allowing you to erase the CD and burn it again with updated information. This evolution tracked closely to ROM development in the early ‘80s.

ROM was memory which was created at the factory and never changed. Should an error be found or the data need to be changed replacement of the device was required. Computer developers would generate their code (data to be stored on the ROM), test it thoroughly, save it to magnetic (typically) or paper tape, and send it off to the manufacturer. Unless a generous expedite fee were paid, you could expect to receive samples of your ROM in only a few weeks. As with the later CDs, some soul devised a way for the developer to “burn” their own ROM and hence the Programmable ROM or PROM was born. If your code was defective, simply correct the code and burn a fresh PROM, discarding the earlier version. Updated PROMs could be generated in a matter of minutes.

Eventually, Erasable PROMs (E-PROMs) were introduced where the developer could expose the device to an ultra-violet light source and in a matter of a few hours and a good suntan later he was able to burn his updated code and try again. E-PROMs were good for development, but were too expensive for production. Finally, in 1983 the Electrically Erasable PROM (EEPROM) was brought to market. The EEPROM was inexpensive and could be erased and re-burned using a simple application run on the computer itself.

ROM is used in the computer as BIOS for the motherboard and all sub-assemblies. Any time you update a components BIOS or firmware you are electronically erasing and re-burning the devices ROM.

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